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dual, 256 - positi on, i 2 c- compatible digital potentiometers data sheet ad5243 / ad5248 rev. b information furnished by analog devices is b elieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. n o license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel : 781.329.4700 www.analog.com fax: 781.461.3113 ? 2004 C 20 12 analog devices, inc. all rights reserved. features 2 - channel, 256 - position potentiometers end - to - end resistance: 2.5 k ? , 10 k ? , 50 k ? , and 100 k ? compact 10 - lead msop (3 mm 4.9 mm) package fast settling time: t s = 5 s typ ical on power - up full read/write of wiper register power - on preset to midscale extra package address decode pins : ad0 and ad1 (ad5248 only) computer software replaces microcontroller in factory programming applications single supply: 2.7 v to 5.5 v low temperature coefficient: 35 ppm/c low power: i dd = 6 a max imum wi de operating temperature: ? 40c to +125c evaluation board available applications systems calibrations electronics level settings mechanical trimmers replacement in new designs permanent factory pcb setting transducer adjustment of pressure, temperature, position, chemical, and optical sensors rf amplifier biasing automotive electronics adjustment gain control and offset adjustment functional block dia grams a1 v dd gnd sda scl w1 wiper register 1 pc interface ad5243 04109-0-001 b1 a2 w2 wiper register 2 b2 figure 1 . ad5243 v dd gnd sda scl ad0 ad1 w1 rdac register 1 address decode serial input register ad5248 b1 w2 rdac register 2 b2 / 8 04109-0-002 figure 2 . ad5248 general description the a d5243 and ad5248 provide a compact 3 mm 4.9 mm packaged solution for dual , 256 - position adjustm ent applications. the ad5243 per form s the same electronic adjust ment function as a 3 - ter minal mechanical potentiometer, and the ad5248 performs the same adjust ment function as a 2 - terminal variable resistor . available in four end - to - end resistance values (2.5 k?, 10 k?, 50 k? , and 100 k?), these low temperature coefficient devices are ideal for high accuracy and stability - variable resistance adjustments. the wip er settings are controllable through the i 2 c - compatible digital interface. the ad5248 has extra package address decode pins , ad0 and ad1, allowing multiple parts to share the same i 2 c , 2 - wire bus on a pcb. the resistance between the wiper and either endp oint of the fixed resistor varies linearly with respect to the digital code transferred into the rdac latch. 1 operating from a 2.7 v to 5.5 v power supply and consuming less than 6 a allows the ad5243/ad5248 to be used in portable battery - operated applica tions. for applications that program the ad5243/ad5258 at the factory, analog devices , inc., offers device programming software running on windows? nt/2000/xp operating systems. this software effectively replaces the need for external i 2 c controllers, whi ch in turn enhances the time to market of systems . an ad5243/ ad5248 evaluation kit and software are available. the kit includes a cable and instruction manual. 1 the terms digital potentiometer , vr , and rdac are used interchangeably.
ad5243/ad5248 data sheet rev. b | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagrams ............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? electrical characteristics: 2.5 k version ................................. 3 ? electrical characteristics: 10 k, 50 k, and 100 k versions .......................................................................................... 4 ? timing characteristics: all versions ......................................... 5 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? pin configurations and function descriptions ........................... 7 ? typical performance characteristics ............................................. 8 ? test circuits ..................................................................................... 12 ? theory of operation ...................................................................... 13 ? programming the variable resistor and voltage ................... 13 ? programming the potentiometer divider ............................... 14 ? esd protection ........................................................................... 14 ? terminal voltage operating range ......................................... 14 ? power-up sequence ................................................................... 14 ? layout and power supply bypassing ....................................... 14 ? constant bias to retain resistance setting ............................. 15 ? i 2 c interface .................................................................................... 16 ? i 2 c compatible, 2-wire serial bus .......................................... 16 ? i 2 c controller programming .................................................... 18 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 19 ? revision history 4/12rev. a to rev. b changes to rheostat operation section, table 7, and table 8 ............................................................................................... 13 changes to voltage output operation section ........................... 14 deleted evaluation board section and figure 45, renumbered sequentially ...................................................................................... 15 changes to table 13 ......................................................................... 17 updated outline dimensions ........................................................ 19 changes to ordering guide ........................................................... 19 4/09rev. 0 to rev. a changes to dc characteristicsrheostat mode parameter and to dc characteristicspotentiometer divider mode parameter, table 1 ................................................................................................. 3 moved figure 3 .................................................................................. 5 updated outline dimensions ........................................................ 19 changes to ordering guide ........................................................... 19 1/04revision 0: initial version
data sheet ad5243/ad5248 rev. b | page 3 of 20 specifications electrical character istics : 2.5 k ? version v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +125c; unless otherwise noted. table 1 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r - dnl r wb , v a = no connect ? 2 0.1 +2 lsb resistor integral nonlinearity 2 r - inl r wb , v a = no connect ? 14 2 + 14 lsb nominal resistor tolerance 3 ?r ab t a = 25c ? 20 +55 % resistance temperatu re coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c wiper resistance r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristics potentiometer divider mode 4 differential nonlinearity 5 dnl ? 1.5 0.1 +1.5 lsb integral nonlinearity 5 inl ? 2 0.6 +2 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full - scale error v wfse code = 0xff ? 14 ? 5 .5 0 lsb zero - scale error v wzse code = 0x00 0 4.5 1 2 lsb resistor terminals voltage range 6 v a , v b , v w gnd v dd v capacitance a, b 7 c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacitance w 7 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 8 i a_sd v dd = 5.5 v 0.01 1 a common - mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance 7 c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a power dissipation 9 p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = midscale 0.02 0.08 %/% dynamic characteristics 10 bandwidth , ? 3 db bw code = 0x80 4.8 mhz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 1 s resistor noise voltage density e n_wb r wb = 1.25 k ? , r s = 0 3.2 nv/ hz 1 typical specifications represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error , r - inl , is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from the ideal between successive tap positions. parts are guaranteed monotonic. 3 v a = v dd , v b = 0 v, wiper (v w ) = no connect. 4 specifications apply to all vrs . 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divider similar to a voltage output digital - to - analog converter (dac). v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6 resistor terminal a, res istor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 7 guaranteed by design , but not subject to production test. 8 measured at the a terminal. the a terminal is open circuited in shutdown mode. 9 p diss is ca lculated from (i dd v dd ). cmos logic level inputs result in minimum power dissipation. 10 all dynamic characteristics use v dd = 5 v.
ad5243/ad5248 data sheet rev. b | page 4 of 20 electrical character istics : 10 k ? , 50 k ? , and 100 k ? versions v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ? 40c < t a < 125c; unless otherwise noted. table 2 . parameter symbol conditions min typ 1 max unit dc characteristics rheostat mode resistor differential nonlinearity 2 r - dnl r wb , v a = no connect ? 1 0.1 +1 lsb resistor integral nonlinearity 2 r - inl r wb , v a = no connect ? 2.5 0.25 +2.5 lsb nominal resistor tolerance 3 ?r ab t a = 25c ? 20 +20 % resistance temperature coefficient (?r ab /r ab )/?t v ab = v dd , wiper = no connect 35 ppm/c wiper resistance r wb code = 0x00, v dd = 5 v 160 200 ? dc characteristics potentiometer divid er mode 4 differential nonlinearity 5 dnl ? 1 0.1 +1 lsb integral nonlinearity 5 inl ? 1 0.3 +1 lsb voltage divider temperature coefficient (?v w /v w )/?t code = 0x80 15 ppm/c full - sca le error v wfse code = 0xff ? 2.5 ? 1 0 lsb zero - scale error v wzse code = 0x00 0 1 2.5 lsb resistor terminals voltage range 6 v a , v b , v w gnd v dd v capacitance a, b 7 c a , c b f = 1 mhz, measured to gnd, code = 0x80 45 pf capacita nce w 7 c w f = 1 mhz, measured to gnd, code = 0x80 60 pf shutdown supply current 8 i a_sd v dd = 5.5 v 0.01 1 a common - mode leakage i cm v a = v b = v dd /2 1 na digital inputs and outputs input logic high v ih v dd = 5 v 2.4 v input logic low v il v dd = 5 v 0.8 v input logic high v ih v dd = 3 v 2.1 v input logic low v il v dd = 3 v 0.6 v input current i il v in = 0 v or 5 v 1 a input capacitance c il 5 pf power supplies power supply range v dd range 2.7 5.5 v supply current i dd v ih = 5 v or v il = 0 v 3.5 6 a power dissipation p diss v ih = 5 v or v il = 0 v, v dd = 5 v 30 w power supply sensitivity pss v dd = 5 v 10%, code = mid scale 0.02 0.08 %/% dynamic characteristics bandwidth , ? 3 db bw r ab = 10 k?/50 k?/100 k?, code = 0x80 600/100/40 khz total harmonic distortion thd w v a = 1 v rms, v b = 0 v, f = 1 khz, r ab = 10 k? 0.1 % v w settling time t s v a = 5 v, v b = 0 v, 1 lsb error band 2 s resistor noise voltage den sity e n_wb r wb = 5 k ? , r s = 0 9 nv/hz 1 typical specifications represent average readings at 25c and v dd = 5 v. 2 resistor position nonlinearity error , r - inl , i s the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. r - dnl measures the relative step change from the ideal between successive tap positions. parts are guaranteed monotonic. 3 v a = v dd , v b = 0 v, wiper (v w ) = no connect. 4 specifications apply to all vrs . 5 inl and dnl are measured at v w with the rdac configured as a potentiometer divide r similar to a voltage output dac . v a = v dd and v b = 0 v. dnl specification limits of 1 lsb maximum are guaranteed monotonic operating conditions. 6 resistor terminal a, resistor terminal b, and resistor terminal w have no limitations on polarity with respect to each other. 7 guaranteed by design , but not subject to production test. 8 measured at the a termi nal. the a terminal is open circuited in shutdown mode.
data sheet ad5243/ad5248 rev. b | page 5 of 20 timing characteristics: all versions v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +125c; unless otherwise noted. table 3. parameter symbol conditions min typ max unit i 2 c interface timing characteristics 1 scl clock frequency f scl 0 400 khz bus-free time between stop and start, t buf t 1 1.3 s hold time (repeated start), t hd;sta t 2 after this period, the first clock pulse is generated. 0.6 s low period of scl clock, t low t 3 1.3 s high period of scl clock, t high t 4 0.6 s setup time for repeated start condition, t su;sta t 5 0.6 s data hold time, t hd;dat 2 t 6 0.9 s data setup time, t su;dat t 7 100 ns fall time of both sda and scl signals, t f t 8 300 ns rise time of both sda and scl signals, t r t 9 300 ns setup time for stop condition, t su;sto t 10 0.6 s 1 see the timing diagrams for the locations of measured va lues (that is, see figure 3 and figure 45 to figure 48). 2 the maximum t hd:dat must be met only if the device does not stretch the low period (t low ) of the scl signal. 04109-0-021 t 1 t 2 t 3 t 8 t 8 t 9 t 9 t 6 t 4 t 7 t 5 t 2 t 10 ps s scl sda p figure 3. i 2 c interface detailed timing diagram
ad5243/ad5248 data sheet rev. b | page 6 of 20 absolute maximu m ratings t a = 25c, unless otherwise noted. table 4 . parameter rating v dd to gnd ? 0.3 v to +7 v v a , v b , v w to gnd v dd terminal current, ax to bx, ax to wx, bx to wx 1 pulsed 20 ma continuous 5 ma digital inputs and output voltage to gnd 0 v to 7 v operating temperature range ? 40c to +125c maximum junction temperatu re (t jmax ) 150c storage temperature ? 65c to +150c lead temperature (soldering, 10 sec) 300c thermal resistance , ja for 10 - lead msop 2 230c/w 1 the m ax imum terminal current is bound by the maximum current handling of the switches, the maxim um power dissipation of the package, and the maximum applied voltage across any two of the a, b, and w terminals at a given resistance. 2 the p ackage power dissipation is (t jmax ? t a )/ ja . stresses above those listed under absolute maximum ratings may c ause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum ratin g conditions for extended periods may affect device reliability. esd caution
data sheet ad5243/ad5248 rev. b | page 7 of 20 pin configurations a nd function descript ions 10 9 8 7 1 2 3 4 b1 a1 w2 w1 b2 a2 sda gnd 6 5 scl v dd top view ad5243 04109-0-027 figure 4 . ad5243 pin configuration 10 9 8 7 1 2 3 4 b1 ad0 w2 w1 b2 ad1 sda gnd 6 5 scl v dd top view ad5248 04109-0-028 figure 5 . ad5248 pin configur ation table 5 . ad5243 pin function descriptions pin no. mnemonic description 1 b1 b1 terminal. 2 a1 a1 terminal. 3 w2 w2 terminal. 4 gnd digital ground. 5 v dd positive power supply. 6 scl serial clock inp ut. positive - edge triggered. 7 sda serial data input/output. 8 a2 a2 terminal. 9 b2 b2 terminal. 10 w1 w1 terminal. table 6 . ad5248 pin function descriptions pin no. mnemonic description 1 b1 b1 terminal. 2 ad0 programmable address bit 0 for multiple package decoding. 3 w2 w2 terminal. 4 gnd digital ground. 5 v dd positive power supply. 6 scl serial clock input. positive - edge triggered. 7 sda serial data input/output. 8 ad1 programmable address bit 1 for multiple package decoding. 9 b2 b2 terminal. 10 w1 w1 terminal.
ad5243/ad5248 data sheet rev. b | page 8 of 20 typical performance characteristics ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-030 v dd = 5.5v t a = 25c r ab = 10k? v dd = 2.7v figure 6. r - inl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rheostat mode dnl (lsb) 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-031 t a = 25c r ab = 10k? v dd = 2.7v v dd = 5.5v figure 7. r - dnl vs. cod e vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode inl (lsb) 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-032 r ab = 10k? v dd = 2.7v t a = ?40c, +25c, +85c, +125c v dd = 5.5v t a = ?40c, +25c, +85c, +125c figure 8 . inl vs. code vs. temperature ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-033 v dd = 2.7v; t a = ?40c, +25c, +85c, +125c r ab = 10k? figure 9 . dnl vs. code vs. temperature ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 potentiometer mode inl (lsb) 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-034 t a = 25c r ab = 10k? v dd = 2.7v v dd = 5.5v figure 10 . inl vs. code vs. supply voltages ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 potentiometer mode dnl (lsb) 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-035 t a = 25c r ab = 10k? v dd = 2.7v v dd = 5.5v figure 11 . dnl vs. code vs. supply voltages
data sheet ad5243/ad5248 rev. b | page 9 of 20 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 rheostat mode inl (lsb) 1.0 1.5 2.0 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-036 r ab = 10k? v dd = 2.7v t a = ?40c, +25c, +85c, +125c v dd = 5.5v t a = ?40c, +25c, +85c, +125 c figure 12 . r - inl vs. code vs. temperature ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 rheostat mode dnl (lsb) 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-037 v dd = 2.7v, 5.5v; t a = ?40c, +25c, +85c, +125c r ab = 10k? figure 13 . r - dnl vs. code vs. temperature ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 fse, full-scale error (lsb) 1.0 1.5 2.0 temperature ( c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 04109-0-038 v dd = 5.5v, v a = 5.0v r ab = 10k? v dd = 2.7v, v a = 2.7v figure 14 . full - scale error vs. tempe rature 0 0.75 1.50 2.25 3.00 3.75 4.50 zse, zero-scale error (lsb) temperature ( c) ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 04109-0-039 v dd = 5.5v, v a = 5.0v r ab = 10k? v dd = 2.7v, v a = 2.7v figure 15 . zero - scale error vs. temperature i dd , supply current ( a) 0.1 1 10 ?40 ?7 26 59 92 125 temperature ( c) 04109-0-040 v dd = 5v v dd = 3v figure 16 . supply current vs. temperature ?20 0 20 40 60 80 100 120 rheostat mode tempco (ppm/ c) 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-041 r ab = 10k? v dd = 2.7v t a = ?40c to +85c, ?40c to +125c v dd = 5.5v t a = ?40c to +85c, ?40c to +125c figure 17 . rheostat mode tempco r wb / t vs. code
ad5243/ad5248 data sheet rev. b | page 10 of 20 ?30 ?20 ?10 0 10 20 potentiometer mode tempco (ppm/ c) 30 40 50 1 2 8 9 6 3 2 6 4 0 1 6 0 1 9 2 2 2 4 2 5 6 code (decimal) 04109-0-042 r ab = 10k? v dd = 2.7v t a = ?40c to +85c, ?40c to +125c v dd = 5.5v t a = ?40c to +85c, ?40c to +125c figure 18 . potentiometer mode tempco v wb / t vs. code ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 10k 1m 100k 10m 04109-0-043 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 19 . gain vs. frequency vs. code, r ab = 2.5 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 04109-0-044 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 20 . gain vs. frequency vs. code, r ab = 10 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 04109-0-045 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 21 . gain vs. frequency vs. code, r ab = 50 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 1k 100k 10k 1m 04109-0-046 0x80 0x40 0x20 0x10 0x08 0x04 0x01 0x02 figure 22 . gain vs. frequency vs. code, r ab = 100 k ? ?60 ?54 ?48 ?42 ?36 ?30 ?24 ?18 ?12 ?6 0 gain (db) frequency (hz) 10k 1k 100k 1m 10m 04109-0-047 100k ? 60khz 50k? 120khz 10k ? 570khz 2.5k? 2.2mhz figure 23 . C 3 db bandwidth at code = 0x80
data sheet ad5243/ad5248 rev. b | page 11 of 20 i dd , supply current (ma) 0.01 1 0.1 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 digital input voltage (v) 04109-0-052 t a = 25c v dd = 2.7v v dd = 5.5v figure 24 . supply current vs. digital input voltage 04109-0-048 scl v w figure 25 . digital feedthrough 04109-0-049 v w1 v w2 figure 26 . digital crosstalk 04109-0-051 v w1 v w2 figure 27 . analog crosstalk 04109-0-053 v w figure 28 . midscale glitch, co de 0x80 to code 0x7f 04109-0-050 scl v w figure 29 . large - signal settling time
ad5243/ad5248 data sheet rev. b | page 12 of 20 test circuits figure 30 through figure 36 illustrate the test circuits that define the test conditions used in the product specification tables (see table 1 and table 2 ) . 04109-0-003 v ms a w b dut v+ v+ = v dd 1lsb = v+/2 n figure 30 . test circuit for potentiometer divider nonlinearity error (inl, dnl) 04109-0-004 no connect i w v ms a w b dut figure 31 . test circuit for resistor position nonlinearity error (rheostat operation : r - inl, r - dnl) 04109-0-005 v ms2 v ms1 v w a w b dut i w = v dd /r nominal r w = [v ms1 ? v ms2 ]/i w figure 32 . test circuit for wiper resistance 04109-0-006 ?v ms % dut ( ) a w b v + ?v dd % ?v ms ?v dd ?v dd v a v ms v+ = v dd 10% psrr (db) = 20 log pss (%/%) = figure 33 . test circuit for power supply sensitivity (pss, pssr) 04109-0-009 +15v ?15v w a 2.5v b v out offset gnd dut ad8610 v in figure 34 . test circuit for gain vs. frequency 04109-0-010 w b v ss to v dd dut i sw code = 0x00 r sw = 0.1v i sw 0.1v figure 35 . test circuit for incremental on resistance w b v cm i cm a nc gnd nc v dd dut nc = no connect 04109-0-011 figure 36 . test circuit for common - mode leakage current
data sheet ad5243/ad5248 rev. b | page 13 of 20 theory of operation the ad5243/ad5248 are 256-position, digitally controlled variable resistor (vr) devices. an internal power-on preset places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. programming the variable resistor and voltage rheostat operation the nominal resistance of the rdac between terminal a and terminal b is available in 2.5 k, 10 k, 50 k, and 100 k. the nominal resistance (r ab ) of the vr has 256 contact points accessed by the wiper terminal and the b terminal contact. the 8-bit data in the rdac latch is decoded to select one of the 256 possible settings. a w b a w b a w b 04109-0-012 figure 37. rheostat mode configuration assuming that a 10 k part is used, the first connection of the wiper starts at the b terminal for data 0x00. because there is a 160 wiper contact resistance, such a connection yields a minimum of 320 (2 160 ) resistance between terminal w and terminal b. the second connection is the first tap point, which corresponds to 359 (r wb = r ab /256 + 2 r w = 39 + 2 160 ) for data 0x01. the third connection is the next tap point, representing 398 (2 39 + 2 160 ) for data 0x02, and so on. each lsb data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,281 (r ab + 2 r w ). d5 d4 d3 d7 d6 d2 d1 d0 rdac latch and decoder r s r s r s r s a w b 04109-0-013 figure 38. ad5243 equivalent rdac circuit the general equation determining the digitally programmed output resistance between w and b is w ab wb rr d dr ???? 2 256 )( (1) where: d is the decimal equivalent of the binary code loaded in the 8-bit rdac register. r ab is the end-to-end resistance. r w is the wiper resistance contributed by the on resistance of the internal switch. in summary, if r ab is 10 k and the a terminal is open circuited, the following output resistance, r wb , is set for the indicated rdac latch codes. table 7. codes and corresponding r wb resistance d (dec) r wb () output state 255 10,281 full scale (r ab ? 1 lsb + 2 r w ) 128 5380 midscale 1 359 1 lsb + 2 r w 0 320 zero scale (wiper contact resistance) note that in the zero-scale condition, a finite wiper resistance of 320 is present. care should be taken to limit the current flow between w and b in this state to a maximum pulse current of no more than 20 ma. otherwise, degradation or possible destruction of the internal switch contact may occur. similar to the mechanical potentiometer, the resistance of the rdac between wiper w and terminal a also produces a digitally controlled complementary resistance, r wa . when these terminals are used, the b terminal can be opened. setting the resistance value for r wa starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. the general equation for this operation is w ab wa rr d dr ??? ? ? 2 256 256 )( (2) when r ab is 10 k and the b terminal is open circuited, the output resistance, r wa , is set according to the rdac latch codes, as listed in table 8. table 8. codes and corresponding r wa resistance d (dec) r wa () output state 255 359 full scale 128 5320 midscale 1 10,280 1 lsb + 2 r w 0 10,320 zero scale typical device-to-device matching is process-lot dependent and may vary by up to 30%. because the resistance element is pro- cessed in thin-film technology, the change in r ab with temperature has a very low temperature coefficient of 35 ppm/c.
ad5243/ad5248 data sheet rev. b | page 14 of 20 programming the pote ntiometer divider voltage output operation the digital potentiometer easily generates a voltage divider at wiper to b and wiper to a , proportional to the input voltage at a to b. unlike the polarity of v dd to gnd, which must be positive, voltage across a to b, w to a, and w to b can be at either polarity. a v i w b v o 04109-0-014 fi gure 39 . potentiometer mode configuration if ignoring the effect of the wiper resistance for approximation, connecting the a terminal to 5 v and the b terminal to ground produces an output voltage at the wiper to b , starting at 0 v up to 1 lsb less than 5 v. each lsb of voltage is equal to the voltage applied across terminal a and terminal b divided by the 256 positions of the potentiometer divider. the general equation defining the output voltage at v w with respect to ground for an y valid input voltage applied to terminal a and terminal b is b a w v d v d d v 256 256 256 ) ( ? + = (3) operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. unlike in the rheostat mode, the output voltage is d ependent mainly on the ratio of the internal resistors , r wa and r wb , not on the absolute values. therefore, the temperature drift reduces to 15 ppm/c. esd protection all digital inputs are protected with a series of input resistors and parallel zener esd structures, as shown in figure 40 and figure 41 . this applies to the sda, scl, ad0, and ad1 digital input pins (ad5248 only). logic 340? gnd 04109-0-015 figure 40 . esd protection of digital pins a, b, w gnd 04109-0-016 figure 41 . esd protection of resistor terminals terminal voltage ope rating range the ad5243/ad5248 v dd and gnd power supply defines the boundary conditions for proper 3 - terminal digital potentiometer operation. supply signals present on the a, b, and w terminals that exceed v dd or gnd are clamped by the internal forward - biased diodes (see figure 42). gnd a w b v dd 04109-0-017 figure 42 . maximum terminal voltages set by v dd and gnd power - up sequence because the es d protection diodes limit the voltage compliance at the a, b, and w terminals (see figure 42 ), it is important to power v dd /gnd before applying voltage to the a, b, and w terminals ; otherwise, the diode is forward - biased such that v dd is powered unintentionally and may affect the rest of the users circuit. the ideal power - up sequence is in the following order: gnd, v dd , digital inputs, and then v a , v b , and v w . the relative order of powering v a , v b , v w , and the digital inputs is no t important , as long as they are powered after v dd /gnd. layout and power sup ply bypassing it is a good practice to employ compact, minimum lead length layout design. the leads to the inputs should be as direct as possible with a minimum conductor length. ground paths should have low resistance and low inductance. similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. supply leads to the device should be bypassed with dis c or chip ceramic capacitors of 0.01 f to 0.1 f. low esr 1 f to 10 f tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see figure 43 ). in addition, n ot e that the digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. v dd gnd v dd c3 10f c1 0.1f ad5243 + 04109-0-018 figure 43 . power supply bypassing
data sheet ad5243/ad5248 rev. b | page 15 of 20 constant bias to ret ain resistance setti ng for users who desire nonvolatility but cannot justify the addi - tional cost of an eemem, the ad5243/ad5248 can be considered low cost alternatives by maintaining a constant bias to retain the wiper setting. the ad5243/ad5248 are designed specifically for low power applications , allowing low power consumption even in battery - operated systems. the graph in figure 44 demonstrates the power consumption from a 3.4 v , 450 mahr li - ion cell phone battery connected to the ad5243/ad5248. the measurement over ti me shows that the device draws approximately 1.3 a and consumes negligible power. over a course of 30 days, the battery is depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself. days battery life depleted (%) 0 90 92 94 96 5 10 15 98 100 102 104 106 108 110 20 25 30 04109-0-019 t a = 25 c figure 44 . battery operating life depletion this demonstrates that constantly biasing the potentiometer can be a practical approach. most portable devices do not require the removal of batteries for the purpose of charging. although the resistance s etting of the ad5243/ad5248 is lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the ad5243/ad5248. if total power is lost, the user should be provided with a means to adjust the setting accordingly.
ad5243/ad5248 data sheet rev. b | page 16 of 20 i 2 c interface i 2 c compatible , 2 - wire serial bus the 2 - wire , i 2 c - compatible serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high - to - low transition on the sda line occurs while scl is high (see figure 45 ). the following byte is the slave address byte, which consists of the slave address followed by an r/ w bit (this b it deter - mines whether data is read from or written to the slave device). the ad5243 has a fixed slave address byte, whereas the ad5248 has two configurable address bits , ad0 and ad1 (see figure 10 ). the slave whose address corre sponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is called the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or r ead from its serial register. if the r/ w bit is high, the master reads from the slave device. on the other hand, if the r/ w bit is low, the master writes to the slave device. 2. in the write mode, the second byte i s the instruction byte. the first bit (msb) of the instruction byte is the rdac subaddress select bit. a logic low selects channel 1 and a logic high selects channel 2. the second msb, sd, is a shutdown bit. a logic high causes an open circuit at terminal a while shorting the wiper to terminal b. this operation yields almost 0 ? in rheostat mode or 0 v in potentiometer mode. it is important to note that the shutdown operation does not disturb the contents of the register. when the ad5243 or ad5248 is bro ug ht out of shutdown, the previ ous setting is applied to the rdac. in addition , during shutdown, new settings can be programmed. when the part is returned from shutdown, the corresponding vr setting is applied to the rdac. the remainder of the bits in the i nstruction byte are dont care bits (see figure 10 ). after acknowledging the instruction byte, the last byte in write mode is the data byte. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bi ts followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 45 and figure 46). 3. in the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the write mode , where there are eight data bits followed by an acknow ledge bit). similarly, the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl (see figure 47 and figure 48 ). note that the c hannel of interest is the one that is previously selected in write mode. i f users need to read the rdac values of both channels, they need to program the first channel in write mode and then change to read mode to read the first channel value. after that, the user must return the device to write mode with the second channel selected and read the second channel value in read mode. it is not necessary for users to issue the frame 3 data b yte in write mode for subse quent readback operation. users should refer to figure 47 and figure 48 for the programming format. 4. after all data bits have been read or written, a stop condition is established by the master. a stop condition is defi ned as a low - to - high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 45 and figure 46 ). in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, which goes high to establish a stop condition (see figure 47 and figure 48 ). a repeated write function provides the user with the flexibility of updat ing the rdac output multiple times after addressing and instructing the part only once. for examp le, after the rdac has acknowledged its slave address and instruction bytes in write mode, the rdac output updates on each successive byte. if different instructions are needed, however, the write/read mode must restart with a new slave address, instruct ion, and data byte. similarly, a repeated read function of the rdac is also allowed.
data sheet ad5243/ad5248 rev. b | page 17 of 20 write mode table 9 . ad5243 write mode s 0 1 0 1 1 1 1 w a a0 sd x x x x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte table 10 . ad5248 write mode s 0 1 0 1 1 ad1 ad0 w a a0 sd x x x x x x a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte instruction byte data byte read mode table 11. ad5243 read mode s 0 1 0 1 1 1 1 r a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte data byte table 12 . ad5248 read mode s 0 1 0 1 1 ad1 ad0 r a d7 d6 d5 d4 d3 d2 d1 d0 a p slave address byte data byte table 13 . sda bits descriptions bit description s start condition. p stop condition. a acknowledge. ad0, ad1 package pin - programmable address bits. x dont care. w write. r read. a0 rdac subaddress select bit. sd shutdown connects wiper to b terminal and open circuits the a terminal. it does not change the contents of the wiper register. d7, d6, d5, d4, d3, d2, d1, d0 data bits.
ad5243/ad5248 data sheet rev. b | page 18 of 20 i 2 c controller programming write bit patterns 04109-0-022 scl start by master sda 01 1 frame 1 slave address byte 01111 frame 2 instruction byte ack by ad5243 r/w a0 sd x x x x 19 d7 d6 d5 d4 d3 ack by ad5243 frame 3 data byte 19 x stop by master 9 d2 d1 d0 ack by ad5243 x figure 45. writing to the rdac registerad5243 04109-0-023 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 instruction byte ack by ad5248 r/w a0 sd x x x x 19 d7 d6 d5 d4 d3 ack by ad5248 frame 3 data byte 19 x stop by master 9 d2 d1 d0 ack by ad5248 x figure 46. writing to the rdac registerad5248 read bit patterns 04109-0-024 scl start by master stop by master sda 01 1 frame 1 slave address byte 01111 frame 2 rdac register ack by ad5243 r/w d7 d6 d4 d3 d2 d1 d0 19 no ack by master 9 d5 figure 47. reading data from a previously selected rdac register in write modead5243 04109-0-025 scl start by master sda 01 1 frame 1 slave address byte 0 1 1 ad1 ad0 frame 2 rdac register ack by ad5248 r/w d7 d6 d4 d3 d2 d1 d0 1 99 d5 stop by master no ack by master figure 48. reading data from a previously selected rdac register in write modead5248 multiple devices on one bu s (applies only to ad5248) figure 49 shows four ad5248 devices on the same serial bus. each has a different slave address because the states of their ad0 and ad1 pins are different. this allows each device on the bus to be written to or read from independently. the master device output bus line drivers are open-drain pull-downs in a fully i 2 c-compatible interface. sda sda ad1 ad0 master scl scl ad5248 sda ad1 ad0 scl ad5248 sda ad1 ad0 scl ad5248 sda 5v r p r p 5v 5v 5v ad1 ad0 scl ad5248 04109-0-026 figure 49. multiple ad5248 devices on one i 2 c bus
data sheet ad5243/ad5248 rev. b | page 19 of 20 outline dimensions compliant to jedec standards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1.10 max 3.10 3.00 2.90 coplanarity 0.10 0.23 0.13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 50 . 10 - lead mini small outline package [msop] (r m - 10) dimensions shown in millimeters ordering guide mode l 1 , 2 r ab temperature package description package option branding ad5243brm2.5 2.5 k ? ? 40c to +125c 10- lead msop rm - 10 d0l ad5243brm10 10 k ? ? 40c to +125c 10 - lead msop rm - 10 d0m ad5243brm10 - rl7 10 k ? ? 40c to +125c 10- lead msop rm - 10 d0m ad5243brm50 50 k ? ? 40c to +125c 10- lead msop rm - 10 d0n ad5243brm50 - rl7 50 k ? ? 40c to +125c 10- lead msop rm - 10 d0n ad5243brm100 100 k ? ? 40c to +125c 10- lead msop rm - 10 d0p ad5243brm100 - rl7 100 k ? ? 40c to +125c 10- lead msop rm - 10 d0p ad5243brmz2.5 2.5 k ? ? 40c to +125c 10- lead msop rm - 10 d9x ad5243brmz2.5 - rl7 2.5 k ? ? 40c to +125c 10- lead msop rm - 10 d9x ad5243brmz10 10 k ? ? 40c to +125c 10- lead msop rm - 10 d0m ad5243brmz10 - rl7 10 k ? ? 40c to +125c 10- lead msop rm - 10 d0m ad5243brmz50 50 k ? ? 40c to +125c 10- lead msop rm - 10 d0n ad5243brmz50 - rl7 50 k ? ? 40c to +125c 10- lead msop rm - 10 d0n ad5243brmz100 100 k ? ? 40c to +125c 10- lead msop rm - 10 d0p ad5243brmz100 - rl7 100 k ? ? 40c to +125c 10 - lead msop rm - 10 d0p eval - ad5243sdz evaluation board ad5248brm2.5 2.5 k ? ? 40c to +125c 10- lead msop rm - 10 d1f ad5248brm2.5 - rl7 2.5 k ? ? 40c to +125c 10- lead msop rm - 10 d1f ad5248brm10 10 k ? ? 40c to +125c 10- lead msop rm - 10 d1g ad5248brm10 - rl7 10 k ? ? 40c to +125c 10- lead msop rm - 10 d1g ad5248brm50 50 k ? ? 40c to +125c 1 0 - lead msop rm - 10 d1h ad5248brm50 - rl7 50 k ? ? 40c to +125c 10- lead msop rm - 10 d1h ad5248brm100 100 k ? ? 40c to +125c 10- lead msop rm - 10 d1j ad5248brm100 - rl7 100 k ? ? 40c to +125c 10- lead msop rm - 10 d1j ad5248brmz2.5 2.5 k ? ? 40c to +125c 10- lead msop rm - 10 d1f ad5248brmz2.5 - rl7 2.5 k ? ? 40c to +125c 10- lead msop rm - 10 d1f ad5248brmz10 10 k ? ? 40c to +125c 10- lead msop rm - 10 d8z ad5248brmz10 - rl7 10 k ? ? 40c to +125c 10- lead msop rm - 10 d8z ad5248brmz50 50 k ? ? 40c to +125 c 10 - lead msop rm - 10 d90 ad5248brmz50 - rl7 50 k ? ? 40c to +125c 10- lead msop rm - 10 d90 ad5248brmz100 100 k ? ? 40c to +125c 10- lead msop rm - 10 d91 ad5248brmz100 - rl7 100 k ? ? 40c to +125c 10- lead msop rm - 10 d91 1 z = rohs compliant part. 2 the evaluation board is shipped with the 10 k ? r ab resistor option; however, the board is compatible with all available resistor value options.
ad5243/ad5248 data sheet rev. b | page 20 of 20 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the p hilips i 2 c patent rights to use these components in an i 2 c system, provided that the system co nforms to the i 2 c standard specification as defined by philips. ? 2004 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04109 - 0 - 4/12(b)

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